EDA related resource

• FPGA-Based Prototyping Methodology
• UVM download
• expression tree https://www.geeksforgeeks.org/dsa/expression-tree/
• ABC
  • ABC pdf
  • abc web
• RDMA 杂谈
• binary machinery
• writing synthesizable verilog
• 全球四大顶级 EDA 会议 DAC（国际设计自动化会议，Design Automation Conference）、ICCAD（国际计算机辅助设计会议，International Conference on Computer Aided Design）、DATE（欧洲设计自动化与测试学术会议，Design, Automation and Test in Europe）和ASP-DAC（亚太地区设计自动化会议，Asia and South Pacific Design Automation Conference）
• Yosys Open Synthesis Suite
• Bus Functional Model (BFM)
• AXI Protocol Overview(from fpagemu: hardware basic)
• Building a basic AXI Master
• CIRCT introduction
• loop in verilog
• for-loop in systemverilog
• nju formal
  • spyglass synopsys
  • JasperGold Candence